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HIGH-VOLTAGE MIXED-SIGNAL IC
65x102 Matrix LCD Controller-Driver
Product Specifications Revision 0.54
OCT 12, 2001
ULTRACHIP
The Coolest LCD Driver. Ever!!
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000
2
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
UC1602I
Single-Chip, Ultra-Low Power Passive Matrix LCD Controller-Driver INTRODUCTION
UC1602I is an advanced high-voltage mixedsignal CMOS IC, especially designed for the display needs of ultra-low power hand-held devices. In addition to low power column and row drivers, these ICs contain all necessary circuits for high-V LCD power supply, bias voltage generation, timing generation and graphics data memory. Advanced circuit design techniques are employed to minimize external component counts and reduce connector size while achieving extremely low power consumption.
FEATURE HIGHLIGHTS
* * Supports I2C 2-wire serial interface and 8bit parallel bus interface. Ultra-low power LCD controller-driver with built-in display RAM and timing generator to support compact LCD module using as few as 5 pins. VDD2/3 voltage range: 2.4V ~ 3.3V VDD1 voltage range: 1.8V ~ 3.3V 4.5V ~ 10.5V LCD VOP range: 6x, built-in self-configuring, charge pump allows the use of low VDD while produce high VLCD for driving LCD. On-chip charge pump pumping capacitors requires only 3 external capacitors. Two multiplexing rates: 1/65, 1/49. Four temperature compensations. Support both high speed parallel interfaces and compact serial interfaces. Flexible data addressing/mapping schemes to support wide ranges of software models and LCD layout placements.
*
*
MAIN APPLICATIONS
* * * Cellular Phones or Smart Phones Pagers or other battery operated messaging devices Battery Powered Portable Instruments
* * * * *
POWER CONSUMPTION
Symbol Conditions VDD : VLCD 2.7V : 8.5V 2.7V : 8.5V 2.4V : 8.5V IDD(tot) 2.4V : 8.5V 2.7V : 8.5V 2.4V : 8.5V
$
Pump 4x 4x 5x 5x 4x 5x
Display pattern Blank Checker Blank Checker Blank/Checker Blank/Checker
LCD loading
Typ. 95
Max.
Unit
65x102, 12nF Panel
$
105 110 122 A 65 70 0.2 1
No load N/A
Sleep Mode (Display Off)
LCD panel capacitance estimated when displaying checker pattern.
Rev. 0.54 10/12/2001
1
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000
ORDERING INFORMATION
Nomenclature UC1602I-PP-M PP: GU: GD: Fn: Packaging Gold bumped, face up Gold bumped, face down Type n TCP film Drivers 65 COM x 102 SEG Mux Rate Supported 1/65, 1/49 Versions G Description
Part Number UC1602I
Memory 65 x 102
General Notes
APPLICATION INFORMATION For improved readability, the specification contains many application data points. When application information is given, it is advisory and does not form part of the specification for the device. BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of UltraChip's delivery. There is no post waffle saw/pack testing performed on individual die. Although the latest modern processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, UltraChip has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, it is the responsibility of the customer to test and quality their application in which the die is to be used. UltraChip assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. LIFE SUPPORT APPLICATIONS These devices are not designed for use in life support appliances, or systems where malfunction of these products can reasonably be expected to result in personal injuries. Customer using or selling these products for use in such applications do so at their own risk.
2
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
BLOCK DIAGRAM
PAGE ADDRESS GENERATOR
ROW ADDRESS GENERATOR
DATA RAM I/O BUFFER
POWER-ON & RESET CONTROL
COLUMN ADDRESS GENERATOR
LEVEL SHIFTER
CLOCK & TIMING GEN.
DISPLAY DATA RAM
CONTROL & STATUS REGISTER
DISPLAY DATA LATCHES COMMAND HOST INTERFACE LEVEL SHIFTERS COLUMN DRIVERS VLCD & BIAS GENERATOR CLCD
CB1
CB2
Rev. 0.54 10/12/2001
ROW DRIVERS
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000
PIN DESCRIPTION
Name Type Pins MAIN POWER SUPPLY VDD1 VDD2 VDD3 PWR VDD1 supplies for display data RAM and digital logic, VDD2 supplies for VLCD/VB generator, VDD3 supplies for VREF and other analog circuits. VDD2/VDD3 should be connected to the same power source. But VDD1 can be connected to a source voltage no higher than VDD2/VDD3. In COG applications, always use separate ITO traces for VDD1, VDD2 and VDD3 to reduce noise coupling. GND Ground. In COG applications, use separate ITO traces to connect VSS and VSS2 to the separate GND pins or to the shared GND pin and minimize both ITO resistance. LCD POWER SUPPLY VB1+ VB1- VB0- VB0+ LCD Offset Voltages. Connect two CB capacitors between VB+ to VB0+ and VB0- to V B-. For optimum operation result, minimize the ITO trace resistance of these nodes. Place CB1 and CB0 on the FPC or COF to reduce I/O pin count by 4. Main LCD Power Supply. When internal VLCD is used, connect these pins together. When external VLCD source is used, connect external VLCD source to VLCD-IN pins and leave VLCD-OUT pins open. A by-pass capacitor CL should be connected between VLCD and VSS2. Minimize the ITO trace resistance in COG applications. Description
VSS VSS2
PWR
VLCD-IN VLCD-OUT
PWR
NOTE Recommended capacitor values: * CB: 150~500x LCD load capacitance or 1.0uF (VBR > 3V), whichever is higher. CL: 20~50x LCD load capacitance or 0.2uF (VBR > VLCD+1V), whichever is higher.
Name C0, ~ C101 RIC R1, R3, ... R63 R2, R4, ...
I/O
Pins
Description LCD DRIVE OUTPUT (UP TO 198 PINS)
HV HV
LCD column driver outputs. Support up to 102 columns. Leave unused drivers open-circuit. LCD icon driver outputs. RIC has two pads. These two pads are used to drive icons. Leave unused drivers open-circuit. LCD row driver outputs. Support up to 64 rows.
HV
Drivers for even and odd row are group into two separate groups along the two sides of the IC. Leave unused drivers open-circuit.
4
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
Name R64
I/O
Pins
Description
Rev. 0.54 10/12/2001
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000 Description CONFIGURATION PINS Parallel/Serial. Serial modes: Parallel modes:
Name
Type
Pins
PS[1:0] VDD1 TP3 TP[2:0] TST[3:1] VDD1 CS0/A0 CS1/A1
C S I I I/O S
"LL": serial (S8) "HL": 8080
"LH": 2-wire serial (I2C) "HH": 6800
For configuration purpose TEST PINS Test control. Connect to GND. Test control. Leave these pins open during normal use. Test I/O pins. Leave these pins open during normal use. HOST INTERFACE Use for configuration purpose. Chip Select or Chip Address. In parallel mode and S8 mode, chip is selected when CS0="L" and CS1="H". In I2C mode, A[1:0] specifies bit 3~2 of UC1602I's device address. When the chip is not selected, D[7:0] will be high impedance. When RST="L", all control registers are re-initialized by their default states and/or by their pin configurations if applicable. When RST is not used, connect the pin to VDD1. Select Control data or Display data for read/write operation. CD pin is not used in I2C modes, connect it to VDD or VSS. "L": Control data "H": Display data WR[1:0] controls the read/write operation of the host interface. In parallel mode, WR[1:0] meaning depends on whether the interface is in the 6800 mode or the 8080 mode. In serial interface modes, these two pins are not used. Connect to VSS. Bi-directional bus for both serial and parallel host interfaces. In S8 mode, connect unused pins to VDD or VSS. In I2C mode, connect D[1:0] to SCK, and D[5:2] to SDA, and D[7:6] to VDD or VSS.
I
RST
I
CD
I
WR0 WR1
I
D0~D7
I/O
D0 D1 D2 D3 D4 D5 D6 D7
PS=1x D0 D1 D2 D3 D4 D5 D6 D7
PS=0x SCK
SDA
-
In I2C mode, SDA and SCK are in open-drain mode. Pull up resistors are required on the bus. In COG applications, be careful to control ITO trace resistance, as it will affect effective output level of SDA.
NOTE *
Unless otherwise specified, connect all unused input pins and control pins to VSS.
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Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
CONTROL REGISTERS
UC1602I contains registers which controls the chip operation. These registers can be modified by commands. The commands supported by UC1602I are described in the next section.
Name: Default:
The Symbolic reference of the register byte. Note that, some symbol names refers to collection of bits (flags) within one register byte. Value after Power-up-Reset and System-Reset. "PIN" means default value depends on the connection of associated configuration pin(s).
Bits Default Description
Name
MR SL CR CA PA BR TC
1 6 8 8 4 2 2
1H 0H 0H 0H 0H 2H 0H
Multiplexing Rate: Number of pixel rows plus icon row. 0: 49 Return Column Address. Display Data RAM Column Address (Used in Host to Display Data RAM access) Display Data RAM Page Address (Used in Host to Display Data RAM access) Bias Ratio. The ratio between VLCD and VD. Temperature Compensation (per oC). 00: 0.0% 01: -0.05% 10: -0.1% 11: -0.2% Gain = VD / VPM Electronic Potential Meter to generate VPM from VREF Operating Modes 10: Sleep 01: (Not used) 11: Normal 00: Reset 1: 65 Start Line. Mapping from Row0 to Display Data RAM.
GN PM OM
2 6 2
3H 10H 0
BZ RS PC
1 1 3
-
Busy with internal processes (reset, changing mode, etc.) OK for Display RAM read/write access. Reset in progress, Host Interface not ready Power Control. PC[0] 0: LCD load < 12nF PC[2:1] 00: External VLCD 10: 5x Pump
07H
1: LCD load > 12nF 01: 4x Pump 11: 6x Pump
APC0
8
6CH
Advanced Program Control. Default value should work fine.
Rev. 0.54 10/12/2001
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000
Name
Bits
Default
Description
DC
3
0H
Display Control: DC[0]: PXV: Pixels Inverse DC[1]: APO: All Pixels ON DC[2]: DE, Display Enable
AC
4
0H
Address Control: AC[0]: WA: Automatic column/page Wrap Around AC[1]: Reserved (always set to 0) AC[2]: PID: PA (page address) auto increment direction (L:+1 H:-1) AC[3]: CUM: Cursor update mode, when CUM=1, CA increment on write only, wrap around suspended
LC
4 0 0 0 0
LCD Layout Control: LC[0]: MSF: MSB First mapping Option LC[1]: Reserved (always set to 0) LC[2]: MX, Mirror X (Column sequence inversion) LC[3]: MY, Mirror Y (Row sequence inversion)
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Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
COMMANDS
The following is a list of host commands support by UC1062I. C/D: W/R: 0: Control, 0: Write Cycle, 1: Data 1: Read Cycle
# Useful Data bits - Don't Care
Command C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Action
Write Data Byte Read Data Byte Get Status Set Column Address LSB Set Column Address MSB Set Mux rate & Temperature Compensation. Set Power Control Set Adv. Program Control (double byte command) Set Start Line Set VREF potential meter (double-byte command) Set RAM Address Control Set Column Mirroring Set All-Pixel-ON Set Inverse Display Set Display ON/OFF Set Page Address Set LCD to RAM Mapping Set Cursor Update Mode System Reset NOP Set LCD Bias Ratio Set/Reset Cursor-Update Mode Set Test Control (double byte command)
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
# # 0 0 0 0 0 # 0 1 # 1 1 1 1 1 1 1 1 1 1 1 1 1 #
# # 0 0 0 0 0 # 1 0 # 0 0 0 0 0 0 1 1 1 1 1 1 1 #
# # 0 0 1 1 1 # # 0 # 0 1 1 1 1 1 0 1 1 1 1 1 1 #
# # 0 1 0 0 1 # # 0 # 0 0 0 0 0 1 0 0 0 0 0 0 0 #
# # 0 # # 0 1 0 # # 0 # 1 0 0 0 1 # # 0 0 0 1 1 0 #
# # 0 # # # # 0 # # 0 # # 0 1 1 1 # # 0 0 0 0 1 1 #
# # 0 # # # # RR # # 0 # # 0 0 1 1 # 0 0 1 1 # 1 TT #
# # 0 # # # # # # 1 # # # # # # # # 0 0 1 # #
Write 1 byte @ PA/CA Read 1 byte @ PA/CA Get Status Summary Set CA[3:0]=D[3:0] Set CA[7:4] =D[3:0] Set MR=D[2] Set TC[1:0]=D[1:0] Set PC[2:0]=D[2:0] Set APC[R][7:0]=D[7:0], where RR = 00, or 01 Set SL[5:0]=D[5:0] Set PM[5:0]=D[5:0] Set GN[1:0]=D[7:6] Set AC[2:0]=D[2:0] Set LC[2]=D0 Set DC[1]=D0 Set DC[0]=D0 Set DC[2]=D0 Set PA[3:0]=D[3:0] Set LC[3:0]=D[3:0] Set AC[3]=1, CR=CA; System Reset sequence No operation Set BR[1:0]= D[1:0] Set AC[3]=D0; if (D0) CR=CA else CA=CR; For testing only. Do not use.
BZ MX DE RS
#
* Other than commands listed above, all other bit patterns result in NOP (No Operation).
Rev. 0.54 10/12/2001
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000
LCD VOLTAGE SETTINGS
MULTIPLEX RATES TC[1:0] 0 1 2 3
Two multiplex rates are supported in UC1602I: 65 or 49. The default is 65 and it can be changed by programming.
BIAS SELECTION
% per C
o
0.0
-0.05
-0.10
-0.20
Table 4: Temperature Compensation
For all TC values, VREF are normalized to 1.2V at 25 oC.
VLCD SELECTION
Bias Ratio (BR) is defined as the ratio between VLCD and VD, i.e. BR = VLCD/VD, where VD is the SEG data signal and its value is | VB1+ - VB1- | The optimum Bias Ratio can be calculated by:
VLCD may be supplied either by internal charge pump or by external power supply. The source of VLCD is controlled by PC[2:1]. When VLCD is generated internally its value has the following relationship with VD:
Mux + 1
UC1602I supports four bias ratios as below.
BR Bias Ratio 0 6 1 7 2 8 3 9
V LCD = BiasRatio x V D
Given VREF = 1.2V at 25 oC, VLCD becomes:
Table 2: BR vs. Mux rates
V LCD BiasRatio x Gain x
BR and MR can both be changed dynamically by software programming.
VD GENERATION
600 + PM x 1 .2 1200
(1)
When PM=0, then equation (1) becomes:
V LCD BiasRatio x Gain x 0.6
LOAD DRIVING STRENGTH
(1b)
VD is generated internally by UC106. The value of VD is determined by three control registers: GN (Gain), PM (Potential Meter), TC (Temperature Compensation) with the following relationship:
V D = Gain x V PM
where VPM is the output of an internal Electronic Potential Meter. The maximum value for VD depends on the value of VDD2. At VDD2 = 2.4V, VD should be kept under 1.2V. The value of VPM is given by:
UC106's drivers and power supply circuits are designed to handle panel capacitance load of 25nF at VLCD=9V when VDD2 >= 2.4V. UC1602I load driving strength is sensitive to ITO impedance of power supply circuits (VDD2, VSS2, VB0/B1, VLCD.) Be sure to minimize the resistance of these ITO traces for COG applications.
POWER SUPPLY CONFIGURATION
VPM
600 + PM = x V REF 1200
The value of Gain is controlled by GN[1:0]. Their relationship is shown below:
GN[1:0] 00 Gain 1.35
UC1602I has built-in charge pump with on-chip pumping capacitors. The number of pump stages used can be programmed by setting PC[2:1] register. Make sure the chip is in Reset mode before changing the value of PC[2:0]. Given the same display quality, the lower the PC[2:1] setting the more efficient is UC1602I, but the weaker is the driving strength. In application, designer is recommended to verify the design with the highest setting first before trying lower settings to achieve better efficiency. Due to the use of fully embedded power supply, built-in power ready detector, and drain circuit, there is no rigid power up or power down sequences for UC1602I controllers when using internal VLCD generator. On the other hand, caution must be exercised when external VLCD source is used. The general rule of thumb is to make sure Display Enable is
Product Specifications
01 1.49
10 1.64
11 1.81
Table 3: Gain vs. GN value VREF TEMPERATURE COMPENSATION
VREF is a temperature compensated reference voltage. VREF increases automatically as ambient temperature cools down. Four (4) different temperature compensated VREF can be selected via pin wiring. The compensation coefficient is given by the following table:
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UC1602I
65x102 Matrix LCD Controller-Drivers
OFF before connecting or disconnecting external VLCD sources.
DISPLAY CONTROLS
LCD DISPLAY CONTROLS
CLOCK & TIMING GENERATOR
There are three display control flags in the control register DC: Display Enable (DE), All-Pixel-ON (APO) and Inverse (PXV). DE has the overriding effect over PXV and APO. DISPLAY ENABLE (DE) Display Enable is controlled by the Set Display ON command. When DE is set to OFF (logic "0"), both column and row drivers will become idle and the chip will put itself into Sleep Mode to conserve power. When the DE is set to ON, the chip will first exit from Sleep mode by restoring the power (VLCD, VD etc.). When the power is restored, column and row drivers will become active. ALL PIXELS ON (APO) When set, this flag will force all column drivers to output On signals, disregarding the data stored in the display buffer. This flag has no effect when Display Enable is OFF and it has no effect on data stored in RAM. INVERSE (PXV) When this flag set to ON, column drivers will output the inverse of the value it received from the display buffer RAM. This flag has no impact on data stored in RAM.
The nominal frequency of UC1602I built-in system clock is 166kHz, the LCD refresh frequency is 80Hz. All required components for the clock oscillator are built-in. No external parts are required.
DRIVER MODES
Row and column drivers can be in either Idle mode or Active mode, controlled by Display Enable flag (DC[2]). When column drivers are in idle mode, their outputs are high-impedance (open circuit). When row drivers are in idle mode, their outputs are connected to VSS.
DRIVER ARRANGEMENTS
The naming conventions are: Rx (where x=1~64) refers to the row driver for the x-th row of pixels on the LCD panel; RIC refers to the icon driver. Row drivers are clustered into "even row drivers" and "odd row drivers", along the two sides of the chip to enhance the symmetry of ITO layout. The mapping of Rx to LCD pixel rows is the same for all MR settings. When MR setting is not 11, leave unused row drivers open.
Rev. 0.54 10/12/2001
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000
RAM W/R EO
R0
R1
R2
C0
C1
Fig. 4 Column and Row Driving Waveform
12
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
HOST INTERFACE
UC1602I series supports several parallel and serial host interface formats.
Bus Bus Type 8080 6800 4-wire (S8) 2-wire (I2C) Access R/W R/W W R/W
Parallel Serial
The timing relationship between UC1602I internal control signal RD, WR and their associated bus actions are shown in the figure below. The generation of UC1602I internal bus control signals WR and RD is shown in the table below.
Bus Type
___ ___ ___ __
Table 5: Host interfaces Choices
8080 6800
WR WR0 !(WR1 & !WR0)
RD WR1 !(WR1 & WR0)
Table 7: WR and RD signal generation DISPLAY RAM DATA TRANSFER
System designers can use either the 8-bit parallel bus to achieve the high data transfer rate, or use serial bus to create LCD modules with as few as 9-pin connectors.
PARALLEL INTERFACE
It is possible to interface UC1602I controllers directly to either an 8080-style MPU bus or a 6800-style MCU bus with the following connection.
Bus Type WR0
___ ___
WR1
___ __
UC1602I Display Data RAM (RAM) read interface is implemented as a two-stage pipe-line. This architecture requires that, every time memory address is modified, either in parallel mode or serial mode, all three commands (Set CA-LSB, Set CA-MSB, Set PA) need to be issued, and a dummy read cycle need to be performed before the actual data can propagate through the pipeline and be read from data port D[7:0]. There is no pipeline in write interface of RAM, and the data is transferred directly from data bus buffer to RAM.
8080 6800
WR
__
RD E
R/W
Table 6: MPU bus control signal interface
CD ___ WR
__
RD D[7:0] LLSB DL DL+K CMSB CLSB Dummy DC DC+1 MMSB MLSB
Write Read Bus Holder Column Address DL L L+K DL+K L+K+1 Dummy C DC C+1 DC+1 C+2 C+3 M
Figure 5: Parallel Interface & Related Internal Signals
Rev. 0.54 10/12/2001
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000 the content of the data been transferred. On each write cycle, 8 bits of data, MSB first, are latched on eight (8) rising SCK edges into an 8-bit data holder. If CD=0, the data byte will be decoded as command. If CD=1, this 8-bit will be treated as data and transferred to proper address in the Display Data RAM at the rising edge of the last SCK pulse. Pin CD is examined when SCK is pulled low for the LSB (D0) of each token.
SERIAL INTERFACE
UC1602I supports two serial modes, 4-wire mode (PS=0), and 2-wire I2C mode (PS=1). The mode of interface is determined during power-up process by the value of PS[1:0].
4-WIER SERIAL INTERFACE (S8)
Only write operations are supported in 4-wire serial mode. Pin CS[1-0] are used for chip select and bus cycle reset. Pin CD is used to determine
CS1/0 SDI SCK CD D7 D6 D5 D4 D3
D2
D1
D0
D7
D6
D5
Figure 6: 4-wire Serial Interface (S8) 2-WIRE SERIAL INTERFACE (I C)
2
When PS[1-0] is set to "LH", UC1602I is configured as a slave receiver/transmitter, for industry standard I2C serial interface. Each UC1602I I2C interface sequence starts with a START condition (S) from the bus master, followed by a sequence header, containing a device address, the direction of transfer (RW,
Write Mode MPU S0111 MPU AAC D 0A 7 10D MPU D A 0
0:Write, 1:Read) and mode of transfer (CD, 0:Control, 1:Data). In this mode, CS[1:0] become A[1:0] and are used to configure UC1602I's device address. WR[1:0] and CD are not used and may be connected to GND.
MPU ... ... A
MPU AP
Read Mode MPU S0111 MPU AAC D 1A 7 10D MPU D A 0 ... ... MPU A MPU NP
Figure 7: 2-wire interface protocol
The direction and content of the bytes following each header byte are fixed for the sequence. To change the direction (R W) or the content type (C D), start a new interface sequence with a new header. After receiving the header, the UC1602I will send out an acknowledge signal (A). Then, depends on the setting of the header, the transmitting device (either the bus master or UC1602I) will
start placing data bits on the serial bus, MSB to LSB, and the sequence will repeat until a STOP signal (P, in WRITE), or a Not Acknowledge (N, in READ mode) is sent by the bus master. Note that, for data read (CD=1), the first byte of data is dummy.
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Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
2-WIRE INTERFACE TIMING
The 2-wire I2C interface is a bidirectional interface. In order to properly communicate between all I2C devices, certain timing protocols need to be satisfied.
resistors. A master or slave device initiates or responds to an action by pulling down the bus. UC1602I is a slave I2C device. In idle mode, the both wires, SDA and SCK are pulled high. When the SDA makes a HIGH to LOW transition while SCK remains high, this is 2 the I C START condition. When the SDA makes a LOW to HIGH transition while SCK remain low, this is I2C STOP condition. In between a START and STOP condition, I2C transmits data bits by toggling SCK while SDA remains stable. These relations are shown in Figure 8.
There are always master and slave devices on an I2C bus. The master device initiates an read or write action to the slave device with an address. The selected slave device to the action transimitting or receiving data. Without any action, the I2C bus are pulled high by two pull-up
START DATA 1
DATA 1
DATA 0
STOP
SDA
SCK
Figure 8. I C bus SDA and SCK timing relation.
2
Each eight-bit of data is followed by an acknowledge pulse from the receiver as shown in Figure 9. The master device will generate an extra pulse during this time. It is the receiving device's responsibility to generate this acknowledge pulse regardless of being a master or slave device. UC1602I generates an
S SCK 1 2 3
acknowledge pulse in the write mode. When the acknowledge pulse is HIGH, UC1602I has received write instruction or data correctly. When the acknowledge pulse is LOW, UC1602I has not correctly received instruction and the master device needs to resend.
8 9
Data Transmitter
Acknowledge Data Receiver
Figure 9. I C bus acknowledge pulse
2
No-Acknowledge
Rev. 0.54 10/12/2001
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000 The table below shows an example of UC1602I to support a 11-pin (or 6-pin, if CLCD and CBx are mounted on FPC or COF), using S8, Write-only interface mode and CD pin for bus control.
Comment Use software Reset exclusively. UC1602I will power up and reset SP="00" to S8 interface mode SDO Not used, Connect to GND On FPC/COF Comment Connect to two capacitors, VB0+, VB0- VB1+, VB1- mounted on FPC as SMD. Interface Comment CS0 (or CS1) Chip select CD Control or Display. SCK Connect to clock SDA Serial Data IN VDD1, VDD2, Use three separate ITO traces to VDD3 one common node. Use two separate ITO to one VSS1 ,VSS2 common node. VLCD To VLCD bypass capacitor Table 10: S8 Interface Example Hard wired RST="H"
SERIAL INTERFACE EXAMPLES
The table below shows an example of UC1602I to support a 9-pin (or 4-pin, if CLCD and CBx are mounted on FPC or COF) interface using I2C.
Hard wired Comment RST="H" Use software Reset exclusively. CA[1:0] ="XX" Chip address UC1602I will power up and reset SP="01" to I2C interface mode on FPC/COF Comment Connect to proper capacitors. VB0+, VB0- These capacitors can be VB1+, VB1- mounted on FPC as SMD. Interface Comment SCK Connect to clock SDA Serial I/O VDD1, VDD2, Use three separate ITO traces to one common node. VDD3 Use two separate ITO to one VSS1 ,VSS2 common node. VLCD To VLCD bypass capacitor Table 9: I2C Interface Example
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Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
DISPLAY DATA RAM
DATA ORGANIZATION
accessed both for Host Interface and for display operations. DISPLAY DATA RAM ADDRESSING A Host Interface (HI) memory access operation starts with specifying Page Address (PA) and Column Address (CA) by issuing Set Page Address and Set Column Address commands. If wrap-around (WA, AC[0]) is OFF (0), CA will stop incrementing after reaching the end of page (102), and system programmers need to set the values of PA and CA explicitly. If WA is ON (1), after CA has reached the end of page (CA=101), CA will be rest to 0 and PA will increment or decrement, depending on the setting of Page Increment Direction (PID, AC[2]). When PA reaches the boundary of RAM (i.e. PA = 0 or 7), PA will be wrapped around to the other end of RAM and continue. ICON DATA ADDRESSING The Icon Page is addressed by explicitly setting PA to 8 (the 9th page). When addressing Icon page, auto wrap-around will be suspended and CA will stop when CA reaches 102.
The display data is one bit per pixel and stored in a dual port static RAM (RAM, for Display Data RAM). The RAM size is 65x102. This array of data bits are further organized into pages of 8 bit slices to facilitate parallel bus interface. At the end of the graphics data, UC1602I contains an 1-bit wide page for icon data. When Mirror X (MX, LC[2]) is OFF, the 1st column of LCD pixels will correspond to the bits of the nd first byte of each page, the 2 column of LCD pixels correspond to the bits of the second byte of each page, etc. MSB FIRST OR LSB FIRST There are two options to map D[7:0] to RAM, MSB first (MSF=1), or LSB first (MSF=0), as illustrated below.
DISPLAY DATA RAM ACCESS
The memory used in UC1602I Display Data RAM (RAM) is a special purpose two port SRAM which allows asynchronous access to both its column and row data. Thus, RAM can be independently
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High-Voltage Mixed-Signal IC
MSF 0 1 D0 D7 D1 D6 D2 D5 D3 D4 D4 D3 D5 D2 D6 D1 D7 D0 D0 D7 D1 D6 D2 D5 D3 D4 D4 D3 D5 D2 D6 D1 D7 D0 D0 D7 D1 D6 D2 D5 D3 D4 D4 D3 D5 D2 D6 D1 D7 D0 D0 D7 D1 D6 D2 D5 D3 D4 D4 D3 D5 D2 D6 D1 D7 D0 D0 D7 D1 D6 D2 D5 D3 D4 D4 D3 D5 D2 D6 D1 D7 D0 D0 D7 D1 D6 D2 D5 D3 D4 D4 D3 D5 D2 D6 D1 D7 D0 D0 D7 D1 D6 D2 D5 D3 D4 D4 D3 D5 D2 D6 D1 D7 D0 D0 D7 D1 D6 D2 D5 D3 D4 D4 D3 D5 D2 D6 D1 D7 D0 D0 D7 Line Adderss 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H C101 C0 C100 C1 C2 C3 C4 C5 C6 C7 0 MY=0 SL=0 SL=16 SL=0 R1 R49 R64 R2 R50 R63 R3 R51 R62 R4 R52 R61 R5 R53 R60 R6 R54 R59 R7 R55 R58 R8 R56 R57 R9 R57 R56 R10 R58 R55 R11 R59 R54 R12 R60 R53 R13 R61 R52 R14 R62 R51 R15 R63 R50 R16 R64 R49 R17 R1 R48 R18 R2 R47 R19 R3 R46 R20 R4 R45 R21 R5 R44 R22 R6 R43 R23 R7 R42 R24 R8 R41 R25 R9 R40 R26 R10 R39 R27 R11 R38 R28 R12 R37 R29 R13 R36 R30 R14 R35 R31 R15 R34 R32 R16 R33 R33 R17 R32 R34 R18 R31 R35 R19 R30 R36 R20 R29 R37 R21 R28 R38 R22 R27 R39 R23 R26 R40 R24 R25 R41 R25 R24 R42 R26 R23 R43 R27 R22 R44 R28 R21 R45 R29 R20 R46 R30 R19 R47 R31 R18 R48 R32 R17 R49 R33 R16 R50 R34 R15 R51 R35 R14 R52 R36 R13 R53 R37 R12 R54 R38 R11 R55 R39 R10 R56 R40 R9 R57 R41 R8 R58 R42 R7 R59 R43 R6 R60 R44 R5 R61 R45 R4 R62 R46 R3 R63 R47 R2 R64 R48 R1 RIC RIC RIC 65 C1 C100 C0 C101 C97 C98 C99
(c)2000
MY=1 SL=0 SL=25 SL=25 R48 R25 R9 R47 R24 R8 R46 R23 R7 R45 R22 R6 R44 R21 R5 R43 R20 R4 R42 R19 R3 R41 R18 R2 R40 R17 R1 R39 R16 --R38 R15 --R37 R14 --R36 R13 --R35 R12 --R34 R11 --R33 R10 --R32 R9 --R31 R8 --R30 R7 --R29 R6 --R28 R5 --R27 R4 --R26 R3 --R25 R2 --R24 R1 --R23 R64 R48* R22 R63 R47 R21 R62 R46 R20 R61 R45 R19 R60 R44 R18 R59 R43 R17 R58 R42 R16 R57 R41 R15 R56 R40 R14 R55 R39 R13 R54 R38 R12 R53 R37 R11 R52 R36 R10 R51 R35 R9 R50 R34 R8 R49 R33 R7 R48 R32 R6 R47 R31 R5 R46 R30 R4 R45 R29 R3 R44 R28 R2 R43 R27 R1 R42 R26 --R41 R25 --R40 R24 --R39 R23 --R38 R22 --R37 R21 --R36 R20 --R35 R19 --R34 R18 --R33 R17 --R32 R16 --R31 R15 --R30 R14 --R29 R13 --R28 R12 --R27 R11 --R26 R10 RIC RIC RIC 49 65 49 MUX
PA[3:0]
0000
Page 0
0001
Page 1
0010
Page 2
0011
Page 3
0100
Page 4
0101
Page 5
0110
Page 6
0111
Page 7
1000
Page 8
MX
C99
C98
C97
C96
C95
C94
C4
C3
18
C2
1
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
MX IMPLEMENTATION
Column Mirroring (MX) is implemented by selecting either (CA) or (101-CA) as the RAM column address. Changing MX affects the data written to the RAM. Since MX has no effect of the data already stored in RAM, changing MX does not have immediate effect on the displayed pattern. To refresh the display, refresh the data stored in RAM after setting MX. DISPLAY SCANNING During each field of display, depends on the setting of MR, row electrodes will be scanned in a fixed pattern at a rate of
(80 x Mux Rate) rows/second.
sequence and the following RAM address generation formula. During the display operation, the RAM line address generation can be mathematically represented as following: For the 1 line period of each field Line = Icon Line (40H) For the 2nd line period of each field Line = SL Otherwise Line = Mod(Line+1, 64) Where Mod is the modular operator, and Line is the bit slice line address of RAM to be outputted to column drivers. Line 0 corresponds to the first bit-slice of data in RAM. The above Line generation formula produce the "loop around" effect as it effectively resets Line to 0 when Line+1 reaches 64. Effects such as page scrolling, page swapping can be emulated by changing SL dynamically. MY IMPLEMENTATION Row Mirroring (MY) is implemented by reversing the mapping order between row electrodes and RAM, i.e. the mathematical address generation formula becomes: For the 1st line period of each field Line = Icon Line (40H) For the 2 line period of each field Line = Mod(SL + MUX-2, 64) where MUX = 65 or 49 Otherwise Line = Mod( Line-1 , 64) Visually, the effect of MY is equivalent to flipping the display upside down. The data stored in display RAM is not affected by MY.
nd st
During each row period, the signal at the column drivers determine the ON/OFF status of the row of pixels being scanned. ROW SCANNING Icon data is always outputted via RIC electrodes st before the 1 row of each field. It is then followed by scanning R1 through Rm, where m may be 64, or 48 depends on the setting of MR. Row electrode scanning orders are not affected by Start Line (SL) or Mirror Y (MY, LC[3]). When MY is 0, the effect of SL having a value K is to change the mapping of R0 to the K-th bit slice of data stored in display RAM. Visually, SL having a non-zero value is equivalent to scrolling LCD display up by SL rows. RAM ADDRESS GENERATION The mapping of the data store in the display SRAM and the scanning electrodes can be obtained by combining the fixed Rm scanning
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(c)2000
RESET & POWER MANAGEMENT
TYPES OF RESET CHANGING OPERATION MODE
UC1602I has two different types of Reset: Power-ON-Reset and System-Reset.
Power-ON-Reset is performed right after VDD1 is connected to power. Power-On-Reset will first wait for about 12mS, depending on the time required for VDD to stabilize, and then trigger the System Reset. System Reset can also be activated by software command or by connecting RST pin to ground.
Two commands will initiate OM transitions: Set Display Enable, and System Reset.
Action Set Display Enable "ON" Set Display Enable "OFF" Reset command RST_ pin pulled "L" Power ON reset Mode Normal Sleep OM 11 10
Reset
00
In the following discussions, Reset means System Reset.
RESET STATUS
Table 12: OM changes
When DC[2] is modified by Set Display Enable, OM will be updated automatically. There is no other action required to enter power saving mode. For maximum energy utilization, Sleep mode is designed to retain charges stored in external capacitors CB0, CB1 and CLCD. To drain these capacitors, use Reset command to activate the on-chip draining circuit. OM changes are synchronized with the edges of UC1602I internal clock. To ensure consistent system states, wait at least 10uS after System Reset or Set Display Enable command.
EXITING POWER SAVE MODES
When UC1602I enters RESET sequence:
* * * *
All non-pin configurable control registers will be reset to their default values. All pin configurable control registers will be reset according to their configuration pins. Operation mode will be "Reset" System Status bits RS and BZ will stay as "1" until the Reset process is completed (for a duration of 3~5uS).
Refer to Control Registers for details of control flags and their default values. Refer to Pin Description for configuration pin definitions. When RS=1, only status read command is processed by UC106. All other commands are ignored. Once entered Reset mode, all control registers will be reset to their default values and capacitors will be discharged. In general it is necessary to set up control registers before transition out of the Reset mode.
OPERATION MODES
UC1602I contains internal logic to check whether VLCD and VD is ready before releasing row and column drivers from their OFF states. When exiting Sleep Mode and Reset Mode, column and row drivers will not be activated until UC1602I internal voltage sources are restored to their proper values.
POWER-UP SEQUENCE
UC1602I has three operating modes (OM): Reset, Normal, Sleep.
Mode OM Host Interface Clock LCD Drivers Charge Pump Draining Circuit Reset 00 Active OFF OFF OFF ON Sleep Normal 10 11 Active Active OFF ON OFF ON OFF ON OFF OFF
UC1602I power-up sequence is simplified by built-in "Power Ready" flags and by the automatic invocation of System-Reset command after Power-ON-Reset. System programmer are only required to wait 4~6 ms before starting to issue commands to UC106. No additional commands or waits are required between enabling of the charge pump, turning on the display drivers, writing to RAM or any other commands.
POWER-DOWN SEQUENCE
To prevent the charge stored in capacitors CB+, CB-, and CLCD from damaging the LCD when VDD is switched off, use Reset mode to enable the built-in charge draining circuit to discharge these external capacitors. UC1602I draining resistance is 1K for both VLCD and VB+. It is recommended to wait 3 x RC for
Table 11: Operating Modes
20
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
VLCD and 1.5 x RC for VB+ before allowing VDD to drop below 2V. For example, if CLCD is 1uF, then the draining time required for VLCD is 3~5mS. UC1602I will not drain VLCD when internal VLCD is not used. System designer should take care to
Turn on VDD
make sure external VLCD source is properly drained off before turning off VDD.
Reset command
Wait 4~6mS
Wait 3~5mS
Set LCD Bias Ratio (BR) Set Gain (GN) Set Potential Meter (PM)
Turn off VDD
Figure 13: Reference Power-Down Sequence
Set Display Enable
Figure 12: Reference Power-up Sequence
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SAMPLE COMMAND SEQUENCES
The following table are host interface examples for various UC1602I operations. Step sequences starting with the same number (such as 2a, 2b, 2c, ...) can be rearranged without affecting the result. Some optional steps have mutual dependencies. Such mutually-dependent optional steps need to be elected or skipped together as a group.
C/D
The type of the interface cycle. Depending on the interface type (parallel or serial). This may be external pin (parallel and serial 8-bit), part of the bit stream (serial 9-bit write) or the internal flag (serial 9-bit read). The direction of data flow of the cycle. It can be either Write (0) or Read (1).
W/R
BZ, OM The status of these flags "during" the operation of the command. (Opt.) Optional item.
POWER-UP SEQUENCE
The only "required" command to initialize UC1602I is Set Display ON. However, many other commands (such as Set APO = 0/1, Set LCD Mapping) and any of the NOP bit patterns can be used for maximum software compatibility with other industry leading LCD controller-drivers. The following command sequence can be performed in parallel 8-bit, I2C or S8 modes. Example 1: Use System Reset command.
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Operation OM BZ Comments
-
-
-
-
-
-
-
-
-
- 0 0 0 0 0 - 0
- 1 0 0 0 0 - 0
- D 1 1 0 1 - 0
- D 0 1 0 0 - 0
- D 1 1 1 0 # 1
- D 0 0 0 0 # 0
- - 1 1 0 0 # 1
- - 0 0 # 0 # #
- - 0 # # 0 # #
- Power-On reset. VDD powering up. Wait ~15mS for VDD to become steady. - Automatic System Reset. - (Opt.) Read Status 0 (Opt.) System Reset # (Opt.) Set Bias Ratio # (Opt.) Set Gain 1 (Opt.) Set PM # # (Opt.) Set Power Control
--
1
-- 00 00 00 00 00 00
1 0 0 0 0 0 0
(Recommended) Use "Read Status" to make sure BZ flag is 0 before issuing any other command. Recommended.
If external VLCD is selected, activate the source here.
0 Note:
0
1
0
1
0
1
1
1
1 Set Display ON
11
0
Example 1 does not require the use of RST pin and therefore is more appropriate for applications where compact connector size is critical.
22
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
Example 2: Use RST pin.
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Operation OM BZ Comments
- 0 0 0 0 0 - 0
- 1 0 0 0 0 - 0
- D 1 1 0 1 - 0
- D 1 1 0 0 - 0
- D 1 1 1 0 # 1
- D 0 0 0 0 # 0
- - 0 1 0 0 # 1
- - 0 0 # 0 # #
- - 1 # # 0 # #
- Hold RST pin to "L" until the external power is stable. - (Opt.) Read Status 0 (Opt.) System Reset # (Opt.) Set Bias Ratio # (Opt.) Set Gain 1 (Opt.) Set PM # # (Opt.) Set Power Control
-- 00 00 00 00 00 00
1 0 0 0 0 0 0 Recommended Recommended
If external VLCD is selected, activate the source here.
0
0
1
0
1
0
1
1
1
1 Set Display ON
11
0
POWER-DOWN SEQUENCES
The following two command sequences can be performed in parallel, I C or S8 modes. Option 1: Use System Reset command.
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Operation OM BZ Comments
2
0 - - Note:
0 - -
1 - -
1 - -
1 - -
0 - -
0 - -
0 - -
1 - -
0 System Reset - (Wait ~3mS) - Turn off VDD
00 00 00
1 0 0
Draining CLCD, CB
Option 1 does not require the use of RST pin and therefore is more appropriate for applications where compact connector size is critical.
Option 2: Use RST pin.
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Operation OM BZ Comments
- -
- -
- -
- -
- -
- -
- -
- -
- -
- Hold RST to "L", wait ~3mS - Turn off VDD
00 00
1 0
Draining CLCD, CB
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PREPARE TO ACCESS DATA RAM
Address control (register AC) flags and some LCD to SRAM mapping (register LC) flags affect how data is stored into the display buffer SRAM => Make proper adjustment to these two registers before writing data to UC1602I display buffer SRAM. These sequence can be performed in parallel 8-bit, I2C or S8 modes. These commands can be performed under any operating mode (OM).
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Operation OM 0 0 1 0 0 0 1 # # # (Opt.) Set Address Control - 0 0 1 1 0 0 # # 0 # (Opt.) Set/clear LCD - Mapping control flags. BZ 0 0 Comments
DATA RAM ACCESS: WRITE
These sequence can be performed in parallel 8-bit, I2C or S8. These commands can be performed under any operating mode (OM).
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Operation OM BZ Comments
1 2 3 4 5
0 0 0 1
0 0 0 0
1 0 0 #
0 0 0 #
1 0 0 #
1 1 0 #
# # # #
# # # #
# # # #
# # # #
Set Page Address Set Column Address MSB Set Column Address LSB Write Display Data (repeat as appropriate) (Return to 1 as necessary, repeat until complete)
- - - - -
0 0 0 0 0
DATA RAM ACCESS: READ
For parallel interface and I2C modes, a dummy Read cycle is required when a Read Data command follows immediately after a Write cycle (either Write Data or Write Control).
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Operation OM BZ Comments
1
X
0
1
0
1
1
#
#
#
# Write cycle (either data or control) - Dummy Read cycle # Read Display Data (repeat as appropriate)
-
0
For example: Commands setting PA and/or CA.
2 3
1 1
1 1
- #
- #
- #
- #
- #
- #
- #
- -
0 0
24
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
DATA RAM ACCESS: CURSOR UPDATE
Cursor can be used to support many flexible user interface designs. Blinking cursor requires frequent update to a limited set of pixels. UC1602I Cursor update mode is designed to facilitate such frequent data RAM updates. Under Cursor Update mode, both the wrap around (CA reset to 0, PA increment or decrement) and CA increment on Read are temporary disabled. These two features allow system designer to minimize the need to update CA and PA registers and allows on-chip RAM to be used in Read-Modify-Write style operations. EXAMPLE 1: CURSOR UPDATE WITH READ-MODIFY-WRITE, PARALLEL INTERFACE OR I C MODE
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Operation OM BZ Comments
2
1
0
0
1
1
1
0
0
0
0
0 Set Cursor-Update mode and set CR=CA - Dummy Read cycle # Read Display Data # Write Display Data (Return to 2 and repeat until the cursor is updated) 0 Clear Cursor Update Mode Return to 1 for next cursor update cycle or continue
-
0
2 3
1 1 1
1 1 0
- # #
- # #
- # #
- # #
- # #
- # #
- # #
- - - - -
0 0 0 0 0
CR tracks where CA should be restored later CA unchanged CA will increment, but will not wrap around Set CA=CR
4
0
0
1
1
1
0
1
1
1
EXAMPLE 2: CURSOR UPDATE WITHOUT READ, ALL INTERFACE MODES
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Operation OM BZ Comments
1
0
0
1
1
1
0
1
1
1
1 Set Cursor-Update mode and set CR=CA # Write Display Data (Return to 2 and repeat until the cursor is updated) 0 Clear Cursor Update Mode Return to 1 for next cursor update cycle or continue
-
0
2 3 4
1
0
#
#
#
#
#
#
#
- - - -
0 0 0 0
CR remembers where CA should be restored later CA will increment but will not wrap around Set CA=CR
0
0
1
1
1
0
1
1
1
ENABLE DISPLAY
The following command sequence can be performed in all interface modes.
# C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 Operation OM BZ Comments
0 0 0 0 Note:
0 0 0 0
0 1 1 1
1 0 0 0
# 1 1 1
# 0 0 0
# 0 0 1
# 1 1 1
# 0 1 1
# # # 1
(Opt.) Set Start Line (Opt.) Set All-Pixel-ON (Opt.) Set Inverse Mode. Set Display ON
- - - 11
0 0 0 0
The order of these steps are not critical. However, for the smoothness of display effect, the above sequence is recommended.
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High-Voltage Mixed-Signal IC
(c)2000
ABSOLUTE MAXIMUM RATINGS
In accordance with IEC134, note 1, 2 and 3.
Symbol Parameter Min. Max. Unit
VDD1 VDD2 VDD3 VLCD VIN / VOUT TOPR TSTR TJ PIC
Logic Supply voltage LCD Generator Supply voltage Analog Circuit Supply voltage LCD Generated voltage Any input/output Operating temperature range Storage temperature Junction temperature Total power dissipation
-0.3 -0.3 -0.3 -0.3 -0.3 -25 -50
+4 +4 +4 +12 VDD + 0.3 +85 +100 +150 250
V V V V V
o o o
C C C
mW
Notes
1. 2. VDD1 based on VSS1 = 0V. VLCD based on VSS2 = 0V. Stress outside values listed may cause permanent damages to the device.
26
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
SPECIFICATIONS
DC CHARACTERISTICS Symbol Parameter Conditions Min. Typ. Max. Unit
VDD1 VDD2 VLCD VB0 VIL VIH VOL VOH IIL IOZ R0(col.) R0(row)
fCLK
Digital Supply voltage Supply for VLCD generation LCD Driving Voltage LCD Bias Voltage Input logic LOW Input logic HIGH Output logic LOW Output logic HIGH Input leakage current Output leakage current Column output impedance Row output impedance Internal clock frequency VLCD = 9.0V VLCD = 9.0V
2.4 2.4 4.5 0.2Vdd 0.8Vdd 0.2Vdd 0.8Vdd 1 2.4 2.4 133 166
3.7 3.7 10.5
V V V V V V V V
A A
4.0 4.0 200
k k kHz
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High-Voltage Mixed-Signal IC
(c)2000
AC CHARACTERISTICS
CD
tAS80
CS0, CS1
tAH80
tCY80 tPWR80, tPWW80 tHPW80
WR0, WR1
0.8VDD
0.2VDD
tDS80
D[7:0] Write
tDH80
tACC80
D[7:0] Read
tOD80
Figure 21: Parallel Bus Timing Characteristics (for 8080 MCU)
o
(VDD=2.4V to 3.0V, Ta= -30 to +85 C)
Symbol tAS80 tAH80 tCY80 tPWR80 tPWW80 tHPW80 tDS80 tDH80 tACC80 tOD80 Signal CD Description Address setup time Address hold time System cycle time Pulse width (read) Pulse width (write) High pulse width Data setup time Data hold time Read access time Output disable time
o
Condition
WR1 WR0 WR0, WR1 D0~D7
CL = 100pF
Min. 25 50 300 120 60 60 40 15 - 10
Max. -
Units ns
- - - - - 140 100
ns ns ns ns ns ns
(VDD=3.0V to 4.0V, Ta= -30 to +85 C)
Symbol tAS80 tAH80 TCY80 tPWR80 tPWW80 tHPW80 tDS80 tDH80 tACC80 tOD80 Signal CD Description Address setup time Address hold time System cycle time Pulse width (read) Pulse width (write) High pulse width Data setup time Data hold time Read access time Output disable time Condition Min. 20 45 166 75 30 30 30 10 - 10 Max. - Units ns
WR1 WR0 WR0, WR1 D0~D7
- - - - - 65 45
ns ns ns ns ns ns
CL = 100pF
28
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
CD
tAS68
CS0, CS1
tAH68
tCY68 tPWR68, tPWW68 tLPW68
WR1
0.8VDD
0.2VDD tDS68 tDH68
D[7:0] Write
tACC68
D[7:0] Read
tOD68
Figure 22: Parallel Bus Timing Characteristics (for 6800 MCU)
o
(VDD=2.4V to 3.0V, Ta= -30 to +85 C)
Symbol tAS68 tAH68 TCY68 tPWR68 tPWW68 tLPW68 tDS68 tDH68 tACC68 tOD68 Signal CD Description Address setup time Address hold time System cycle time Pulse width (read) Pulse width (write) Low pulse width Data setup time Data hold time Read access time Output disable time
o
Condition
WR1
D0~D7
CL = 100pF
Min. 25 50 300 120 60 60 40 15 - 10
Max. -
Units ns
- - - - - 140 100
ns ns ns ns ns ns
(VDD=3.0V to 4.0V, Ta= -30 to +85 C)
Symbol tAS68 tAH68 TCY68 tPWR68 tPWW68 tLPW68 tDS68 tDH68 tACC68 tOD68 Signal CD Description Address setup time Address hold time System cycle time Pulse width (read) Pulse width (write) Low pulse width Data setup time Data hold time Read access time Output disable time Condition Min. 20 45 166 75 30 30 30 10 - 10 Max. - Units ns
WR1
D0~D7
- - - - - 70 50
ns ns ns ns ns ns
CL = 100pF
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High-Voltage Mixed-Signal IC
(c)2000
tCSS8
CS0 CS1
tCHS8 tCDHS8
CD
tCDSS8 tWLS8
SCK
tWHS8
tCYS8 0.2VDD 0.8VDD tDSS8 tDHS8
SDI (Input)
Figure 23: Serial Bus (S8 mode) Timing Characteristics
o
(VDD=2.4V to 3.0V, Ta= -30 to +85 C)
Symbol tCSS8 tCHS8 TCDSS8 tCDHS8 tCYS8 tWHS8 tWLS8 tDSS8 tDHS8 Signal CS Description CS setup time CS hold time CD setup time CD hold time SCK clock cycle SCK high width SCK low width Data setup time Data hold time
o
Condition
CD SCK
SDA
Min. 150 150 15 10 250 100 100 90 90
Max. -
Units ns
- -
ns ns
-
ns
(VDD=3.0V to 4.0V, Ta= -30 to +85 C)
Symbol tCSS8 tCHS8 tCDSS8 tCDHS8 tCYS8 tWHS8 tWLS8 tDSS8 tDHS8 Signal CS Description CS setup time CS hold time CD setup time CD hold time SCK clock cycle SCK high width SCK low width Data setup time Data hold time Condition Min. 100 100 10 5 200 75 75 50 50 Max. - Units ns
CD SCK
- -
ns ns
SDA
-
ns
30
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
tWLS9
SCK
tWHS9
tCYS9 0.2VDD 0.8VDD tODS9 tACS9
tACS9
SDO (Output)
tDSS9
SDI (Input)
tDHS9
Figure 24: Serial Bus (I C mode) Timing Characteristics
o
2
(VDD=2.4V to 3.0V, Ta= -30 to +85 C)
Symbol tCYS9 tWHS9 tWLS9 tDSS9 tDHS9 tACS9 tODS9 Signal SCK Description Serial I/O clock cycle SCK high width SCK low width Data setup time Data hold time Read access time Output disable time
o
Condition
Min.
Max.
Units ns
SDA SDA
ns CL = 100pF ns
(VDD=3.0V to 4.0V, Ta= -30 to +85 C)
Symbol tCYS9 tWHS9 tWLS9 tDSS9 tDHS9 tACS9 tODS9 Signal SCK Description Serial I/O clock cycle SCK high width SCK low width Data setup time Data hold time Read access time Output disable time Condition Min. Max. Units ns
SDA SDA
ns CL = 100pF ns
Rev. 0.54 10/12/2001
31
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000
tRW RST
Figure 25: Reset Characteristics
o
(VDD=2.4V to 3.0V, Ta= -30 to +85 C)
Symbol tRW Signal RST Description Reset low pulse width
o
Condition
Min. 1000
Max. -
Units ns
(VDD=3.0V to 4.0V, Ta= -30 to +85 C)
Symbol tRW Signal RST Description Reset low pulse width Condition Min. 500 Max. - Units ns
32
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
PHYSICAL DIMENSIONS
Rev. 0.54 10/12/2001
33
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000
Y BX BY # Pin X Y BX BY
#
Pin
X
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
DUMMY1 R21 R23 R25 R27 R29 R31 R33 R35 R37 R39 R41 R43 R45 R47 R49 DUMMY2 R51 R53 R55 R57 R59 R61 R63 RIC CS0 CS1 VDD1 TP3 RST CD WR0 WR1 VDD1 D0 D1 D2 D3 D4 D5 D6 D7 VDD1 VDD1 VDD1
-3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3500.7 -3327.6 -3272.6 -3217.6 -3162.6 -3107.6 -3052.6 -2997.6 -2942.6 -2859.9 -2789.9 -2719.9 -2649.9 -2579.9 -2509.9 -2439.9 -2369.9 -2299.9 -2229.9 -2159.9 -2089.9 -2019.9 -1949.9 -1879.9 -1809.9 -1739.9 -1669.8 -1599.8 -1529.9
447.0 385.0 330.0 275.0 220.0 165.0 110.0 55.0 0.0 -55.0 -110.0 -165.0 -220.0 -275.0 -330.0 -385.0 -447.0 -420.5 -420.5 -420.5 -420.5 -420.5 -420.5 -420.5 -420.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5
100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 35 35 35 35 35 35 35 35 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50
51 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 51 100 100 100 100 100 100 100 100 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80
46 VDD2 47 VDD2 48 VDD2 49 VDD2 50 VDD3 51 VSS2 52 VSS2 53 VSS2 54 VSS2 55 VSS 56 VSS 57 VSS 58 VSS 59 TST3 60 TST2 61 TST1 62 VB1+ 63 VB1+ 64 VB1+ 65 PS0 66 VDD1 67 PS1 68 VB169 VB170 VB171 TP2 72 TP1 73 TP0 74 VB075 VB076 VB077 VB078 VB0+ 79 VB0+ 80 VB0+ 81 VB0+ 82 VLCDOUT 83 VLCDIN 84 VLCDOUT 85 VLCDIN 86 VDD2 87 VDD2 88 R64 89 R62 90 R60
-1389.8 -1319.8 -1249.8 -1179.9 -1039.9 -622.6 -552.6 -482.6 -412.6 -342.6 -272.6 -202.6 -132.6 -62.6 77.4 217.4 357.6 427.6 497.6 637.6 777.6 847.6 987.6 1057.6 1127.6 1267.6 1407.6 1547.6 1688.6 1758.6 1828.6 1898.6 2038.6 2108.6 2178.6 2248.6 2388.6 2528.6 2668.6 2738.6 2808.6 2878.5 2942.6 2997.6 3052.6
-440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -440.5 -420.5 -420.5 -420.5
50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 50 35 35 35
80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 100 100 100
34
Product Specifications
UC1602I
65x102 Matrix LCD Controller-Drivers
#
Pin
X
Y
BX
BY
#
Pin
X
Y
BX
BY
91 R58 92 R56 93 R54 94 R52 95 R50 96 DUMMY3 97 R48 98 R46 99 R44 100 R42 101 R40 102 R38 103 R36 104 R34 105 R32 106 R30 107 R28 108 R26 109 R24 110 R22 111 R20 112 DUMMY4 113 R18 114 R16 115 R14 116 R12 117 R10 118 R8 119 R6 120 R4 121 R2 122 RIC 123 C0 124 C1 125 C2 126 C3 127 C4 128 C5 129 C6 130 C7 131 C8 132 C9 133 C10 134 C11 135 C12
3107.6 3162.6 3217.6 3272.6 3327.6 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3500.7 3327.4 3272.4 3217.4 3162.4 3107.4 3052.4 2997.4 2942.4 2887.4 2832.4 2777.4 2722.4 2667.4 2612.4 2557.4 2502.4 2447.4 2392.4 2337.4 2282.4 2227.4 2172.4 2117.4
-420.5 -420.5 -420.5 -420.5 -420.5 -447.0 -385.0 -330.0 -275.0 -220.0 -165.0 -110.0 -55.0 0.0 55.0 110.0 165.0 220.0 275.0 330.0 385.0 447.0 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5
35 35 35 35 35 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35
100 100 100 100 100 51 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 51 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100
136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57
2062.4 2007.4 1952.4 1897.4 1842.4 1787.4 1732.4 1677.4 1622.4 1567.4 1512.4 1457.4 1402.4 1347.4 1292.4 1237.4 1182.4 1127.4 1072.4 1017.4 962.4 907.4 852.4 797.4 742.4 687.4 632.4 577.4 522.4 467.4 412.4 357.4 302.4 247.4 192.4 137.4 82.4 27.4 -27.6 -82.6 -137.6 -192.6 -247.6 -302.6 -357.6
420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5
35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35
100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100
Rev. 0.54 10/12/2001
35
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)2000
Y BX BY # Pin X Y BX BY
#
Pin
X
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226
C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 R1 R3
-412.6 -467.6 -522.6 -577.6 -632.6 -687.6 -742.6 -797.6 -852.6 -907.6 -962.6 -1017.6 -1072.6 -1127.6 -1182.6 -1237.6 -1292.6 -1347.6 -1402.6 -1457.6 -1512.6 -1567.6 -1622.6 -1677.6 -1732.6 -1787.6 -1842.6 -1897.6 -1952.6 -2007.6 -2062.6 -2117.6 -2172.6 -2227.6 -2282.6 -2337.6 -2392.6 -2447.6 -2502.6 -2557.6 -2612.6 -2667.6 -2722.6 -2777.6 -2832.6 -2887.6
420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5
35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35
100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100
227 228 229 230 231 232 233 234
R5 R7 R9 R11 R13 R15 R17 R19
-2942.6 -2997.6 -3052.6 -3107.6 -3162.6 -3217.6 -3272.6 -3327.6
420.5 420.5 420.5 420.5 420.5 420.5 420.5 420.5
35 35 35 35 35 35 35 35
100 100 100 100 100 100 100 100
GOLD BUMP SUMMARY Type W L Spacing
HV LV/PWR
35 50
100 80
20 20
* W refers to the side along the edge of chip. * All numbers in uM.
ALIGNMENT MARKS Shape X Y Size
Circle Circle
196 6975
43 43
45 45
36
Product Specifications

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